This invention relates to thin film transistors, thin film transistor arrays and to a method of preparing the same.
It has been known heretofore to utilize thin film transistors and particularly an array of thin film transistors to control and drive display panels such as, for example, liquid crystal displays, electroluminescent mediums, and the like. Thin film transistors in this application offer an attractive substitute to the utilization of silicon technology because of the size limitation problems associated with that technology. A large number of thin film transistors can be prepared within any given size area in a density satisfactory for pictorial presentation. Examples of thin film transistors and associated display panels are set forth in U.S. Pat. Nos. 4,040,073 and 4,042,854.
Fabrication of thin film transistor arrays requires the generation of well-defined geometric patterns of metals, semiconductors and insulators. These are deposited in layers to form the transistor structures and circuit interconnections. Patterns can be generated by shadow masking or photolithographic methods. The first, a popular classic method, relies on a series of mechanical masks to define pattern geometries while shielding the remainder of the substrate from the deposition source. The photolithographic method is attractive for cost effective fabrication of large area circuits containing a high density of components.
It is known by those working in the field of thin film transistors that devices having more suitable characteristics are prepared when the interfaces between the various layers of the thin film transistors are prepared in a single vacuum pump-down. This is especially true of the layers which form the interface with the semiconductive layer of the thin film transistor. It is thought that the reason for this is that a freshly prepared clean surface, when forming the interface with the semiconductive layer, is desirable without being previously subjected to ambient conditions which may result in impurities or some form of degradation occurring to the surface structure. Thus, it is impossible to achieve a thin film transistor by the single pump-down technique where photolithographic techniques are employed in the fabrication of the layers next adjacent to the semiconductive layer. In the past, single pump-down techniques have been employed wherein a multiple number of shadow masks are employed within the vacuum system in order to deposit the proper shape of the different components of the thin film transistor during the single pump-down. This creates many problems because the multiple use of shadow masks has built-in limitations such as high initial capital expenditure, low ultimate panel size, and low resolution of the product. Further, when one shadow mask is moved out of position between the substrate and the source of the material being deposited and a second moved in place, a registration problem employing very close tolerances is present. When it is considered that in a thin film transistor array at least 2500 thin film transistors are prepared per square inch of area, this registration problem is thereby greatly magnified.
It is therefore an object of this invention to provide a method of preparing thin film transistor arrays wherein the various layers are fabricated by a single pump-down technique without the use of multiple shadow mask steps.
______________________________________ PRIOR ART STATEMENT ______________________________________ F. C. Luo U.S. Pat. No. 4,040,073 Aug. 2, 1977 F. C. Luo U.S. Pat. No. 4,042,854 Aug. 16, 1977 M. W. Cresswell U.S. Pat. No. 4,086,127 Aug. 25, 1978 D. J. Page et al U.S. Pat. No. 3,669,661 June 13, 1972 ______________________________________
Luo U.S. Pat. No. 4,040,073--A double gated thin film field effect transistor in which cadmium selenide is the semiconductor material. A thin layer of indium is provided on either side of the cadmium selenide conducting channel and after annealing enhances the transconductance of the device and reduces trapping of charge in the semiconductor. The source and drain contacts of the device are a combination of an indium layer and a copper layer which improve the performance of the device.
Luo U.S. Pat. No. 4,042,854--A large area integrated solid-state flat panel display is detailed in which thin film transistor addressing and drive circuitry is provided at each individual picture point with a display medium. The preferred display medium is an electroluminescent phosphor layer. An insulating layer of laminated photoresist is disposed over all electrical circuit elements except the electroluminescent drive electrodes.
M. W. Cresswell U.S. Pat. No. 4,086,127--An improved method of fabricating apertured deposition masks is disclosed, with the masks being used in the fabrication of thin film deposited electronic components such as transistors. The masks comprise a core portion with a metal layer provided on a relief side of the core and a metal layer provided on the defining side of the core. The relief side metal layer and the core of the mask are further resist delineated, selectively plated and etched differentially providing a mask preform in which the defining side metal layer is left intact. A narrow width radiation beam is then directed upon closely spaced portions of the defining side metal layer to selectively cut through the defining side metal layer providing the desired space apertures separated by a narrow bridge portion of the defining side metal layer.
Page et al U.S. Pat. No. 3,669,661--A process for producing a thin film transistor comprising, disposing a layer of a spacer material on one surface of a substrate, disposing a layer of a metal on said layer of spacing material, coating at least a portion of said metal layer with a layer of a photoresist material, exposing a pattern on said layer of photoresist material, developing said pattern on said layer of photoresist material, etching said pattern through to said one surface of the substrate, disposing said substrate in a vacuum chamber and sequentially vacuum depositing a plurality of materials through said etched pattern onto said surface of the substrate.